W631GG6KB
The MRS command to Non-MRS command delay, t MOD is required for the DRAM to update the
features, except DLL reset, and is the minimum time required from a MRS command to a non-MRS
command excluding NOP and DES shown in Figure 4.
T0
T1
T2
Ta0
Ta1
Ta2
Ta3
Ta4
Tb0
Tb1
Tb2
CK#
CK
Command
Address
VALID
VALID
VALID
VALID
VALID
VALID
MRS
VALID
NOP/DES
VALID
NOP/DES
VALID
NOP/DES
VALID
NOP/DES
VALID
NOP/DES
VALID
VALID
VALID
VALID
VALID
CKE
Settings
Old settings
Rtt_Nom ENABLED prior and/or after MRS command
Updating Settings
t MOD
New Settings
ODT
VALID
VALID
ODTLoff+1
VALID
Rtt_Nom DISABLED prior and/or after MRS command
ODT
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
TIME BREAK
DON'T CARE
Figure 4 – t MOD Timing
The mode register contents can be changed using the same command and timing requirements
during normal operation as long as the DRAM is in idle state, i.e., all banks are in the precharged state
with t RP satisfied, all data bursts are completed and CKE is high prior to writing into the mode register.
If the Rtt_Nom Feature is enabled in the Mode Register prior and/or after a MRS command, the ODT
signal must continuously be registered LOW ensuring R TT is in an off state prior to the MRS
command. The ODT signal may be registered high after t MOD has expired. If the Rtt_Nom feature is
disabled in the Mode Register prior and after a MRS command, the ODT signal can be registered
either LOW or HIGH before, during and after the MRS command. The mode registers are divided into
various fields depending on the functionality and/or modes.
Publication Release Date: Dec. 09, 2013
Revision A05
- 16 -
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